1. Field of the Invention
The present invention relates to a Voltage Controlled Oscillator (VCO), and more particularly, to a VCO that is not affected by the variations of the process and the bias voltage source.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional VCO 100. The VCO 100 comprises a reference current source module 110 and a clock signal generating module 120. The reference current source module 110 functions to generate reference currents IBIAS and I1, as well as the voltages VA and VB. The clock signal generating module 120 generates a clock signal CLK with a frequency corresponding to the level of the voltages VA and VB.
The reference current source module 110 comprises P-type Metal Oxide Semiconductor (PMOS) transistors QP1 and QP2, and N-type Metal Oxide Semiconductor (NMOS) transistors QN1 and QN2. The source (first end) of transistor QP1 is coupled to the bias voltage source VDD; the gate (control end) of the transistor QP1 is coupled to the gate of the transistor QP2; the drain (second end) of the transistor QP1 is coupled to the drain of the transistor QN1. The source (first end) of the transistor QP2 is coupled to the bias voltage source VDD; the gate (control end) of transistor QP2 is coupled to the gate of the transistor QP1; the drain (second end) of the transistor QP2 is coupled to the drain of the transistor QN2. The source (first end) of the transistor QN1 is coupled to the bias voltage source VSS (ground end); the gate (control end) of the transistor QN1 is utilized to receive the reference voltage VREF; the drain (second end) of transistor QN1 is coupled to the drain of the transistor QP1. The source (first end) of the transistor QN2 is coupled to the bias voltage source VSS; the gate (control end) of transistor QN2 is coupled to the drain of transistor QP2; the drain (second end) of transistor QN2 is coupled to the drain of transistor QP2.
The transistor QN1 receives the reference voltage VREF and drains the current IBIAS, with the magnitude corresponding to the voltage level of the reference voltage VREF, from the transistor QP1. The transistors QP2 and QN2 form a current mirror for generating the current I1 and the corresponding control voltages VA and VB, where the current I1 is a replica of the current IBIAS. Hence, the voltages VA and VB can then drive the current source of the clock signal generator 120 to generate a current with the same magnitude as the current IBIAS, and further generate the clock signal CLK with the frequency corresponding to the current generated by the current source of the clock signal generator 120.
However, the threshold voltage level of the Metal Oxide Semiconductor (MOS) transistor is influenced by the process variation. According to the current generating formula of the NMOS transistor:I=K(VGS−VTH)2  (1);where K represents a constant, VGS represents the voltage difference between the gate and the source of the NMOS transistor, and VTH represents the threshold voltage of the NMOS transistor, the current IBIAS being drained by the transistor QN1 of the reference current source module 110 can be calculated from the above formula as below:IBIAS=K(VREF−VSS−VTH)2  (2).
From formula (2), it can be seen that even in the presence of constant reference voltage VREF, the reference current IBIAS is still dependent on the threshold voltage VTH and the bias voltage source VSS, consequently affecting the magnitude of the replicated current I1 and the subsequently generated voltages VA and VB. Therefore, since the current generated by the clock signal generating module 120 is controlled by the voltages VA and VB, the frequency of the output clock signal CLK is inevitably affected, causing great inconvenience.